1. 1. 5 volts per EIA/JESD8-6 and select from the options > within that specification. 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Updated for Intel ® Quartus Prime Design Suite: 19. 1. The BCM84885 is a highly integrated solution combining digital adaptive equalizers, ADCs, phase-locked loops, line drivers, encoders, decoders, echo cancelers, crosstalk cancelers, and all required support circuitry. Loading Application. NVMe-MI technology provides an industry standard for management of NVMe devices in-band. 3 that describe these levels allow voltages well above 5V, but I don't know of any 1. // Documentation Portal . PMA Registers 5. ,Ltd E-mail: ip-sales@design-gateway. GMII Electrical Specification IEEE Interim Meeting, San Diego, January 1997 Dave Fifield 1-408-721-7937 fifield@lan. Cat5 Twisted Pair Media Interface VMDS-10446 VSC8514-11 Datasheet Revision 4. The modules are capable of operating with XGMII interface widths of 32 or 64 bits. 3. 60 6. After the 10 Gbps data is extracted from the four lanes, it must be formatted in a XGMII interface. 3-2008, defines the 32-bit data and 4-bit wide control character. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. At the Tampa meeting I intend to propose that we just adopt the logic family that the XGMII uses (we might have to put a note in about termination schemes as the MDIO is multi-drop). Debug Steps: 1. The PCS IP is engineered to be quickly and easily integrated into any SoC, and to connect seamlessly to a Cadence or third-party MAC through a demultiplexed XGMII (64-bit data, 8-bit control, single clock-edge interface). The 10G Ethernet PCS/PMA core is designed to be attached to the Xilinx IP 10G Ethernet MAC core over XGMII. Download Core Submit Issue. 3. 8. The waveform below shows a DLLP packet. Optional 802. Xilinx has 10G/25G Ethernet Subsystem IP core. On the opposite side a pair of XGMII interfaces are used to transfer frames between the nfmac10g and the PCS/PMA (or XAUI) core. 5. AUTOSAR Introduction - Part 2 21-Jul-2021. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. "JUST" <smile>. Similarly, the XGMII bus corresponds to 10 Gigabit network. All transmit data and control. These specs were defined by the SFF MSA industry group. In case of conflicts, the PCI-Express Base Specification shall supersede the PIPE spec. 25GMII is similiar to XGMII. SD Cards are now available in four standard storage capacities. com Features See Reference Design Manual • 10 Gbps Ethernet • 10G PHY interface: 64-bit XGMII interface at 156. The columns are divided into test parameters and results. XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between. 3, Clause 47. The CoaXPress-over-Fiber Bridge IP Core allows to connect a CoaXPress IP Core to an XGMII (10 Gbps Media Independent Interface) bus inside an FPGA. The Reduced Gigabit Media Independent Interface (RGMII) module provides an RGMII interface to an existing Ethernet MAC design with a GMII or TBI interface, for example the Gigabit Ethernet MAC (GEM) available from Cadence Design Foundry. The PCS IP is engineered to be quickly and easily integrated into any SoC, and to connect seamlessly to a Cadence or third-party MAC through a demultiplexed XGMII (64-bit data, 8-bit control, single clock-edge interface). 5x faster (modified) 2. It can also be used as a serial communication bus between the PowerQUICC™ MPC8313E and other peripherals such as through a. 5V tolerance seems an unnecessary burden. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. Other Parts Discussed in Thread: DP83867E. After PHY finishes the initialization, XGMII sends Idle code instead of Fault code. LLC or other MAC client. 4 PHYs defined in IEEE Std 802. XGMII signaling is based on the HSTL class 1 single-ended I/O standard, which. The XGMII interface defines the 32-bit data and 4-bit wide control character clocked between the MAC/RS and the soft PCS at both the positive and negative edge (double data rate – DDR) of the 156. 5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide. Figure 1. If you set the value of the Ethernet PCS interface parameter in the CPRI parameter editor to GMII, your IP core includes this interface. Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer. Connection to the SerDes is through a configu-rable 16-, 20-, 32-, 40-, or 64-bit interface. At the transmit side of the XAUI interface, the data and control characters are converted within the XGXS into an 8B/10B encoded data stream. LL Ethernet 10G MAC Operating Modes 1. USXGMII - Multiple Network ports over a Single SERDES. Hot Swap Schroff cPCI backplanes fulfill the requirements for Basic Hot Swap of the Hot Swap Specification PICMG 2. 1 R2. 3 that describe these levels allow voltages well above 5V, but I don't know of any 1. and added specification for 10/100 MII operation. Reconfiguration Signals 6. ) • 1. I see three alternatives that would allow us to go forward to > TF ballot. Front-Light Manager. Application. 125Gbps for the XAUI interface. MAC. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User GuideIP is needed to interface the Transceiver with the XGMII compliant MAC. The Full-Speed card supports SPI, 1-bit SD and the 4-bit SD transfer modes at the full cloc k range of 0-25MHz. The host layer access to the Controller IP for Automotive is through industry-standard AXI or AHB interfaces when the DMA is being used or through an external FIFO interface. High-level overview. 10Gb Ethernet Core Designed to the Draft 4. XGMII. 3-2008, defines the 32-bit data and 4-bit wide control character. 3125 Gb/s. 3ae 10 Gigabit Ethernet Summary n The XGMII coding proposal is stable n The EIA/JEDEC SSTL_2 standard can be referenced for the XGMII electrical specification n The timing proposal presented herein is a starting point for further discussion 10-gigabit media-independent interface (XGMII) The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. (MAC) core, which can be configured in XGMII and 10GBASE-R modes. SD 4. This solution is designed to the IEEE 802. 5. AXI-4 or Avalon streaming with 32-bit data path at 312. Functional Description 5. 25 MHz interface clock. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of. At the Tampa meeting I intend to propose that we just adopt the logic family that the XGMII uses (we might have to put a note in about termination schemes as the MDIO is multi-drop). 3 MAC and Reconciliation Sublayer (RS). Reference HSTL at 1. 1. Therefore, it is necessary to complete the conversion of GMII to XGMII interface in firmware. The primary. Figure 3: 10GBASE-X PHY Structure. In each table, each row describes a test case. MAU. 125GBaud/s PCS = Physical Coding Sublayer PMA = Physical Medium Attachment PMD = Physical Medium Dependent (not for all PHYs) XFI XFI (Not specified in IEEE Std 802. Previous definition/implementations cover single (SGMII) and quad (QSGMII) options. 3) 10 Gb/s Serial Electrical Interface Bit serial @ 10Gb/s 64B/66B encoded - 10. - XGMII Interface (64-bit single clock edge) - POS-L3 like Interface for core logic side. Avalon® -MM Interface Signals 6. 25 MHz interface clock. e. The XgmiiSource drives XGMII traffic into a design. 1 XGMII Controller Interface 3. XFP光模块标准定义于2002年左右，其内部的收和发方向都带有CDR电路。. This is not related to the API info. USGMII supports eight 10M/100M/1G network ports over 10Gbps SERDES between MAC and PHY. • Operate in both half and full duplex and at all port speeds. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Table of Contents IPUG115_1. Transceiver Status and Transceiver Clock Status Signals 6. 3-2008 clause 48 State Machines. NOTE: BRCM had a PHY but is changed speeds internally from 10. Overview. XGMII/GMII/RGMII: Source And Data Centered I/O Timing Modes; Supports Jumbo Packet (9600 byte maximum) Operation. PHY register map Original: PDF P1394a P1394a 32-bit 64-bit 1A16 S100 EIA-364-B: 2004 - Not Available. License: LGPL. With a mixture of 100Mbps and 1GbE nodes, system designers prefer to develop common, reusable platforms that support both types of nodes. 4. 5. PCS) IP GT IP Serial. For D1. 5 Gb/s and 5 Gb/s as well as 10 Gb/s. LAN の主流であるイーサネットで初めて WAN での利用を前提とした技術を含む [1] 。. Reference HSTL at 1. Table 20. 3125 Gbit/s) • Data throughput is reduced: • inter-frame gaps are increased through extended operation of MPCP, which accounts for FEC parity insertion • Extra IDLEs are deleted in PCS and used to insert FEC partiyLow Power FPGAs. About LL Ethernet 10G MAC x 1. 5. 10GBASE-KR is an Ethernet defined interface intended to enable 10. With the inclusion of the XAUI interface, the 10 GMAC core can now support 10. - XGMII Interface (64-bit single clock edge) - POS-L3 like Interface for core logic side - Wishbone Interface for control 2. They call this feature AQRate. 15. 本文非原创，摘自：Media Independent Interface Media Independent Interface ( MII)，媒体独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Check MAC PHY XGMII interface signals, no data sent out from MAC. Small Form-factor Pluggable (SFP) is a compact, hot-pluggable network interface module format used for both telecommunication and data communications applications. For more information on XAUI, please refer. Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included. The Intel® Stratix® 10 devices contain a combination of GX, GXT, or GXE channels, in addition to the. The MAC core along with FIFO-core and SPI4/AXI-DMA enginesUSXGMII Subsystem. 3125 Gbps serial line rate with 64B/66B encoding 10GBASE-KR and 1000BASE-KX is the electrical backplane physical layer implementation for the 10 Gigabit and 1 Gigabit Ethernet link defined in clause 72 and clause 70. 4. Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). ) • 1. 5G, 5G, and 10G. 100G only has 1 data interface. Features 2. The names, trademarks and file systems used are listed in Table 1 (below). Unidirectional. In this demo, the FiFo_wrapper_top module provides this interface. MAC – PHY XLGMII or CGMII Interface. Device Speed Grade Support 2. Text: PHY devices via 10-Gbps media independent interface (XGMII) or 10-Gbps attachment unit interface (XAUI) Management data input/output. 3125 Gbps). So I don't think there's an easy way to connect 100G and 25G. 5. This block contains the signals TXD (64-bits) (Transmit data), TXC (8-bits) (Transmit control), RXD (64-bits) (Receive data), and RXC (8-bits) (Receive control). There needs to be some way to allow alternate voltages for this interface and still be standards compliant. Interface Signals 7. 3ae として標準化された。. However, the Altera implementation uses a wider bus interface in connecting a. However, if the XGMII is not implemented, a conforming implementation must behave functionally as though the RS and XGMII were present. Introduction. 2 and XAUI. The current generation of 10 Gigabit Ethernet components uses XGMII, another parallel interface designed for faster speeds. Core data width is the width of the data path connected to the USXGMII IP. I see three alternatives that would allow us to go forward to > TF ballot. 7. But HSTL has more usage for high speed interface than just XGMII. According to IEEE802. 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the USXGMII_SPEED register. 5. In order to connect a 10-Gigabit Ethernet MAC to an off-chip PHY device, an XGMII inter-face is used. 3. 7. As far as I understand, of those 72 pins, only 64 are. If is test the pcs/pma with 'pcs_loopback = 1' , everything works fine. Supports 10-Gigabit Fibre Channel (10. 5Gb/s 8B/10B encoded - 3. Actually - I should amend this answer - XGMII isn't the correct protocol, I think I'm thinking of 10GBASE-R. Inter-Packet Gap Generation and Insertion 4. GMII Electrical Interface Specification Merge the MII electrical specifications in terms of input and output buffer strengths, TTL Level signalling and compatibility with 5V and 3. we should see DLLP packets on the interface. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. Use Case ‘Front Light Management’: Exchange Type of Front Light. 25 MHz interface clock. 25 MHz interface clock. Status Signals. The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802. 2023年11月1日 閲覧。 ^ “QSGMII Specification” (2009年7月20日). . A gigabit interface converter ( GBIC) is a standard for transceivers, first defined in 1995 and commonly used with Gigabit Ethernet and Fibre Channel for some time. The next packet type on the interface will be initial flow control credits i. I have however been just a functional person and just a technical person. > > 1. Software Architecture – AUTOSAR Defined Interfaces. 5G/5G/10Gb Ethernet) PHY standard devices. 3 designed for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board (PCB). Section Content Features Release Information LL. 1G/2. (3) The WAN interface sublayer (WIS) implements the OC-192 framing and scrambling functions. Simulation and verification. The 10 Gigabit Ethernet PCS/PMA (10GBASE-R) is a no charge Xilinx LogiCORE which provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10. 4 Standard, 2. 5Gbps Ethernet core. Host Interface Speed Data width # Pins Clock Frequency Transmission Specification QSGMII 4x ≤1. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. 1. The IP core is compatible with the RGMII specification v2. PHY /Link interface specification , . 25MHz PCS layer XGMII interface implemented as 64-bit (single data rate) SDR interface at 156. Implements 802. 802. Basically, you can think of the SFP+ to BASE-T module as a media converter - it receives 10GBASE-R on one end, and produces 10GBASE-T on the other end, and vise versa. So you never really see DDR XGMII. Designed to Dune Networks RXAUI specification. Inter-Packet Gap Generation and Insertion 4. When TCP/IP network is applied in. It's an attempt to realize the Open RAN concept. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. The generic nature of this interface facilitates mapping the CoaXPress signaling into the. The Serial Gigabit Media Independent Interface ( SGMII) is a sequel of MII, a standard interface used to connect an Ethernet MAC-block to a PHY. XGMII interface in my view will be short lived. Therefore, it is necessary to complete the conversion of GMII to XGMII interface in firmware. to the PCS synchronization specification. 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Updated for Intel ® Quartus Prime Design Suite: 19. The Client-side interface is a 64-bit AXI-S and comes with a 64-bit XGMII interfaces on the PHY side. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 interface device. arm is only willing to license the relevant amba specification to you on condition that you accept all of the terms in this licence. In order to connect a 10-Gigabit Ethernet MAC to an off-chip PHY device, an XGMII inter-face is used. Presentation. These published antenna patterns and associated Institute of. 3 81. AUTOSAR Interface. Media-Independent Interface（MII、媒体独立インタフェース）は、イーサネットにおいて、MAC (データリンク層デバイス)とPHY (物理層デバイス)とを接続するためのインタフェース。本稿では以下の拡張版を含めて記述する。 The XGMII interface defines the 32-bit data and 4-bit wide control character clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156. I see three alternatives that would allow us to go forward to > TF ballot. Return to the SSTL specifications of Draft 1. Core10GMAC supports standard Ethernet interfaces such as the 10 Gbps attachment unit interface (XAUI) and the 10 Gbps reduced attachment unit interface (RXAUI). Release Information 2. 1. Additional info: Design done, FPGA proven, Specification done. XGMII. Overview 2. The XGMII interface defines the 32-bit data and 4-bit wide control character clocked between the MAC/RS and the soft PCS at both the positive and negative edge (double data rate – DDR) of the 156. This specification defines two types of SDIO cards. A second version of the SDIO card is the Low-Speed SDIO card. On the opposite side a pair of XGMII interfaces are used to transfer frames between the nfmac10g and the PCS/PMA (or XAUI) core. Reference industry standard electrical specifications Interface Locations Management 32 data bits, 4 control bits, one clock, for transmit 32 data bits, 4 control bits, one clock, for receive Dual Data Rate (DDR) signaling, with data and control driven and sampled on both rising edge and falling edge of clock Clock Control Data[A/B] Data[A] Data[B] Host Interface Speed Data width # Pins Clock Frequency Transmission Specification QSGMII 4x ≤1. RGMII. Return to the SSTL specifications of Draft 1. The next packet type on the interface will be initial flow control credits i. 2 V or 2. Calibration 8. In the 10G Ethernet segment, the Universal Serial 10G Media Independent Interface (USXGMII) IP core from Microchip enables building 10GBASE-R solutions on PolarFire. – Make MDIO/MDC part of each optional interface (XGMII, XAUI, XSBI, SUPI) • Any device with one of these interfaces would have to also implement MDIO/MDCIEEE 1588v2 Timestamp Interface Signals 7. What i want to do is i want to feed the PCS with xgmii_tx signals, connect the txn/txp to rxn/rxp respectively and monitor the xgmii_rx signals whether they are the same as xgmii_tx. Introduction. I see three alternatives that would allow us to go forward to > TF ballot. The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping. Reconfiguration Signals 6. 15Introduction. Each channel operates from 1. Interface (XGMII) 46. 4. Is there a reference design for for SGMII to GMII core at 2. AXI4-Lite $;, &URVVEDU ,3 AXI4-Lite 1G Ethernet GMII Interface PCS IP /LQH 5DWH 6ZLWFKLQJ /RJLF. The 10GEMAC core is designed to the IEEE 802. Reference industry standard electrical specifications Interface Locations Management 32 data bits, 4 control bits, one clock, for transmit 32 data bits, 4 control bits, one clock, for. 0 Cards use the UHS-II bus interface, which features two rows of pins rather than the single row found in UHS-I. standard FR-4 material. 1. An SFP interface on networking hardware is a modular slot for a media-specific transceiver, such as for a fiber-optic cable. You are required to use an external PHY device to. PHY 8. The Barrel Shifter looks for the start of frame delimiters on 32-bit boundary and re-aligns the data on 64-bit boundary. reference design for SGMII at 2. Interface (XGMII) 46. 3 Clause 46 ratified specification enabling a variety of PHY and MAC chips from different vendors to talk the exact same protocol. GMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in. 3ae specification, the 10Gb Ethernet MAC (10 GMAC) core includes the option of either a parallel 10 Gigabit Media Independent Interface (XGMII) or a serial 10 Gigabit Attachment Unit Interface (XAUI). The shared logic is configured to be included in the example design. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. Table 13. Operating Speed and Status Signals The XAUI PHY uses the XGMII interface to connect to the IEEE802. semi-formal notation to model SoS architectures with. Inter-Frame GAP. Interface”. Return to the SSTL specifications of Draft 1. 3. 8. f) Modified Intellectual Property statement to address incorporation of IP from multiple sources. IEEE 802. On the user side a pair of AXI4-Stream (one master and one slave) interfaces are used to send and receive Ethernet frames from/to the user logic. Each lane contains 8 data plus 1 control bits. 5GPII Implementation as shown does not require much incremental logic Does not preclude implementations that directly map XGMII into PCS Diagram above for IEEE functional specification purposes only 1000BASE-X PHY 2. 14. (2) The XGMII extender sublayer (XGXS) extends the distance of XGMII when used with XUAI and provides the data conversion between XGMII and XAUI. This guide and its associated documents provide recommendations on the use of the _DSD (Device Specific Data) object as defined in the ACPI Specification . The XGMII is a low-speed parallel interface for short range (approximately 2”) interconnects. All forum topics; Previous Topic; Next Topic; 4 Replies 4. 25 MHz interface clock. In total the interface is 74 bits wide. 3-2008, defines the 32-bit data and 4-bit wide control character. Avalon® -MM Interface Signals 6. Reference HSTL at 1. IEEE 802. XGMII signaling is based on the HSTL class 1 single-ended I/O standard, which. WishBone compliant: Yes. 25 Gbps line rate to achieve 10-Gbps data rate. Table 4. Higher layers. 3125 Gbps serial line rate with 64B/66B encoding 10GBASE-KR and 1000BASE-KX is the electrical backplane physical layer implementation for the 10 Gigabit and 1 Gigabit Ethernet link defined in clause 72 and clause 70. e. RGMII uses four-bit wide transmit and receive datapaths, each with its own source synchronous clock. 1G/10GbE PHY Register Definitions 5. 5 volts per EIA/JESD8-6 and select from the options > within that specification. 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto. (MAC), PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T PHY standard devices. 5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, JESD8-6” (1995年8月1日). USXGMII Subsystem. 3125 Gbps serial single channel PHY over a backplane. 6 Functional block diagramHow is data transferred from the XAUI to the User interface? A8. Return to the SSTL specifications of Draft 1. Maps packets between XGMII format and PMA service interface format. 3ae-2002). FPGA. In this demo, the FiFo_wrapper_top module provides this interface. • Once in PCS_Test, there is a problem if the MAC signals LPI over the XGMII interface since this can initiate a transition to QUIET before the Link Partner PHY is ready. 25 Mbps. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. Core data width is the width of the data path connected to the USXGMII IP. Local fault happens, all data sent by client user logic are dropped. 3 media access control (MAC) and reconciliation sublayer (RS). This is the ACPI _DSD Implementation Guide. 5. Provides metadata about the API. For Ethernet backplane applications, XGMII compliant 10GBASEKR_PHY soft IP is developed. RGMII. 7. . These documents describe the technical characteristics of the antenna panels on the GPS Block IIR and Block IIR-M satellites. XAUI uses four full-duplex serial links operating at 3. 1. 3-2008 specification. MAC control. 3 standard. It really isn't right for the technologies we will be using for these chips. In computer networking, Gigabit Ethernet ( GbE or 1 GigE) is the term applied to transmitting Ethernet frames at a rate of a gigabit per second. 10 GIGABIT ETHERNET SGMII supports a single 10M/100M/1G network port over 1,25Gbps SERDES between MAC and PHY, while QSGMII supports four 10M/100M/1G network ports over 5Gbps SERDES between MAC and PHY. Status Signals 6. 2 PCIE Interface 9 2 PRODUCT SPECIFICATIONS 10 2. 4. 8. Design Example MAC Variant PHY Development Kit 10GBase-R Ethernet 10G Native PHY Intel Arria 10 GX Transceiver SI. The BCM84885 is a highly integrated solution combining digital adaptive equalizers, ADCs, phase-locked loops, line drivers, encoders, decoders, echo cancelers, crosstalk cancelers, and all required support circuitry. 1. The code-group synchronization is achieved upon th e reception of four /K28. 1858. • The TX state machines needs a check to prevent this from happening. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 24, 2020 Product Specification Rev1. 3ae-2002 specification requires the XAUI PHY link to support a 10 Gbps data rate at the XGMII interface and four lanes each at 3. O-RAN can. 125 Gbps at the PMD interface. The 10 Gigabit Media Independent Interface (XGMII) is an interface standard that uses 72 data pins for both RX and TX. XFI and SFI electrical specifications respectively apply to XFP and SFP+ system front port optical modules. 08-19-2019 07:57 PM - edited 08-20-2019 07:59 PM. XGMII & XAUI Relationship to ISO/IEC Open Systems Interconnection (OSI) Reference Model & IEEE 802. interface is the XGMII that is defined in Clause 46. The system data width, that is, the width of the interface to the user logic, is c onfigured as 64 bits. 3125 Gb/s link. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and. It consists of pairs of Txdata, Rxdata, and Rx Ref Clk data pins. 2. Session. XGMII Signals 6. status instance: The stp screenshot shows that both channel 0 and 1 are ready with resets de-asserted. 75 Gbps raw data trans-mission capacity. interface is the XGMII that is defined in Clause 46. Rockchip RK3588 datasheet. 1 2 Document Number: DSP0222 3 Date: 2009-07-21 4 Version: 1. Between the MAC and the PHY is the XGMII, or 10 Gigabit Media Independent Interface. 4.